An analog signal comparator is a common functional building block for numerous analog electrical circuits. A hysteretic signal comparator has a hysteresis loop around its reference signal and is, for example, commonly employed in a feedback electrical control circuit to avoid, in the absence of such a hysteresis loop, undesirable excessive oscillations of a controlled signal around its target value.
FIG. A1 illustrates a prior art U.S. Pat. No. 6,229,350 entitled “Accurate, fast, and user programmable hysteretic comparator” by Ricon-Mora et al, hereinafter referred to as U.S. Pat. No. 6,229,350. FIG. A1 illustrates the prior art hysteretic comparator 1 and FIG. A2 illustrates its signal input/output (I/O) characteristics 2. FIG. A2 applies to any hysteretic comparator. The key I/O signals of the prior art hysteretic comparator 1 are a pair of input signals VINA and VINB and a 2-level output signal VOT. To those skilled in the art, in reference to input signal VINB the VOT vs. VINA characteristics of FIG. A2 exhibit a level transition around VINA=VINB with a hysteresis window of Vhys=2*ΔV.
The prior art hysteretic comparator 1 has the following major functional blocks coupled to one another:                A Differential_Input_Stage for differentially converting the input signal pair VINA and VINB into intermediate current signals.        A Summing_Node and an Output_Gain_Stage for converting and amplifying the intermediate current signals into the final 2-level output signal VOT.        A Steerable_offset_current_generator for generating and injecting, through its Current_steering_switch, an offset current into the Differential_Input_Stage thus producing the hysteresis window of Vhys in the VOT vs. VINA characteristics. A Signal_inverter is included to convert VOT into differential control signals required internally by the Steerable_offset_current_generator. Notice that Vhys is further made user programmable through a “Vcontrol” signal applied to the Steerable_offset_current_generator.        Current_mirrors, rooted in a current source “IBIAS”, to supply a number of bias currents required by the Differential_Input_Stage and the Steerable_offset_current_generator.        
As is known to those skilled in the art, the hysteresis window Vhys of the prior art hysteretic comparator 1 is governed by the following equations:
                                          V            hys                    =                                    2              ⁢                                                          ⁢              Δ              ⁢                                                          ⁢              V                        =                                                            I                                      (                    offset                    )                                                                    G                                      m                    ⁡                                          (                      input                      )                                                                                  =                              V                control                                                    ⁢                                  ⁢        where                            (        1        )                                          I                      (            offset            )                          =                              G                          m              ⁡                              (                offset                )                                              *                      V                          (              control              )                                                          (        2        )                                          G          m                =                                            2              ⁢                                                          ⁢                              I                BIAS                                                                    V                GS                            -                              V                th                                              =                                    2              ⁢                                                          ⁢                              I                BIAS                            *              Transistor_Size              *                              K                np                                                                        (        3        )                                          K          np                =                              electron            /            hole_mobility                    *                      C            ox                                              (        4        )            
In the above equations, Gm(input) refers to the transconductance of the differential transistor pair Q2 and Q5 within the Differential_Input_Stage. Gm(offset) refers to the transconductance of the differential transistors Q16, Q17, Q26 and Q27 within the Steerable_offset_current_generator. Gm refers to the transconductance of a generic transistor. VGS and Vth refer respectively to the gate-source voltage and threshold voltage of a generic transistor. Knp is a transistor device parameter sensitive to its numerous fabrication processing tolerances. Cox is the gate oxide capacitance per area.
To be an accurate hysteretic comparator, Vhys should be fabricated with tight tolerance and should exhibit low sensitivity to environmental variations such as temperature. From the above equations (1)-(4) it can be seen that the fractional variation of Vhys tracks that of Gm(input) and Gm(offset). Furthermore, any mismatch of Gm amongst the transistor pairs (for example, between Q2 and Q5) would cause an additional variation of Vhys. While this phenomenon applies to both bipolar and MOS transistors, the degree of Vhys variation becomes especially serious with CMOS transistors. Unlike bipolar transistors, the Gm of a CMOS transistor is small and Gm of CMOS transistors do not match as well. In the prior art, for good matching and large transconductance the size of each of the differential CMOS transistors Q16, Q17, Q26, Q27 must become similar in size as each of the input CMOS transistors Q2, Q5. That means a large integrated circuit (IC) die area would be consumed to implement a simple comparator function, an expensive and unfeasible proposition. Therefore, there exists a need to create a simple hysteretic comparator with an accurate hysteresis window Vhys without consuming a large IC die area.